Insulator-semiconductor interfaces are the major workhorse of the Si semiconductor industry. Integration levels of several million metal-oxide-semiconductor (MOS) devices using a minimum feature size &lt;0.3 .mu.m are commonplace. For compound semiconductors, Schottky gates have been used as gate electrodes. Source and drain regions of submicron devices are realized self aligned to the gate by ion implantation in both Si and GaAs very large scale integration (VLSI). The gate structure and, more specifically, the insulator-semiconductor interface must withstand elevated temperatures (700.degree. C.) during thermal processing, in particular during activation of ion implants. The corresponding fabrication techniques and material systems for Si MOSFETs and GaAs Schottky gate FETs are well known to those skilled in the art.
For MOS structures based on compound semiconductors, prior art, for instance M. Passlack et al., Appl. Phys. Lett., vol. 68, 1099 (1996), Appl. Phys. Lett., vol. 68, 3605 (1996), and Appl. Phys. Lett., vol. 69, 302 (1996), U.S. Pat. No. 5,451,548, entitled "Electron Beam Deposition of Gallium Oxide Thin Films using a Single Purity Crystal Source", issued Sep. 19, 1995, and U.S. Pat. No. 5,550,089, entitled "Gallium Oxide Coatings for Optoelectronic Devices Using Electron Beam Evaporation of a High Purity Single Crystal Gd.sub.3 Ga.sub.5 O.sub.12 Source", issued Aug. 27, 1996, reported that functional oxide III-V semiconductor interfaces are fabricated by in-situ deposition of a specific insulating layer (e.g. gallium oxide such as Ga.sub.2 O.sub.3) on gallium arsenide (GaAs) based semiconductor epitaxial layers while maintaining an ultra-high vacuum. The technique provided gallium oxide films with substantial Gd.sub.2 O.sub.3 and Gd incorporation which increased towards the oxide surface. Full accessibility of the GaAs band gap and interface state densities D.sub.it in the low 10.sup.10 cm.sup.-2 eV.sup.-1 range were demonstrated. The use of an SiO.sub.2 cap layer maintained the integrity of the oxide-GaAs interface during rapid thermal annealing of up to 800.degree. C. However, the use of a SiO.sub.2 cap layer is incompatible with manufacturable processes as described in the following. The use of a SiO.sub.2 cap results in rapid degradation of the oxide-GaAs interface above a temperature of 600.degree. C. when Gd free Ga.sub.2 O.sub.3 films comprise the gate oxide. Note that a Gd free Ga.sub.2 O.sub.3 is required for stable and reliable device operation and a process to fabricate Gd free Ga.sub.2 O.sub.3 films is disclosed in U.S. Pat. No. 5,597,768 entitled "Method of Forming a Ga.sub.2 O.sub.3 Dielectric Layer", issued Jan. 28, 1997. Further, metal cap layers which conserve the oxide-semiconductor interface are required for a manufacturable self-aligned gate process. Processes using dummy gates are not considered to be manufacturable since the fabrication process is substantially complicated and the integration density is limited.
Prior art also describes a method of making a GaAs MOSFET device using ion implantation (Proc. IEEE International Electron Devices Meeting, pp. 943-945 (1996)). The device, however, does not use a self aligned gate technique and thus, is not manufacturable.
Accordingly, it would be highly desirable to provide a method of thermal processing for a self aligned metal-oxide-compound semiconductor gate structure which conserves a low D.sub.it oxide-compound semiconductor structure in particular during activation of ion implants, and a method which is compatible with the requirements in large volume production of highly integrated compound semiconductor MOSFET circuits.
It is a purpose of the present invention to provide a new and improved method of thermal processing for a self-aligned metal-oxide-compound semiconductor gate structure.
It is another purpose of the present invention to provide a new and improved method to conserve a low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure during thermal processing, e.g. during activation of implants, for a self-aligned metal-oxide-compound semiconductor gate structure.
It is a further purpose of the present invention to provide a new and improved method to conserve a low D.sub.it metal-Ga.sub.2 O.sub.3 -compound semiconductor structure during thermal processing, e.g. during activation of implants, for a self-aligned metal-oxide-compound semiconductor gate structure which is fully compatible with the requirements and established processes in large volume production of highly integrated compound semiconductor circuits.
It is a further purpose of the invention to provide a new and improved method to conserve a low D.sub.it metal-Ga.sub.2 O.sub.3 GaAs structure during thermal processing, e.g. during activation of implants, for a self-aligned metal-oxide-compound semiconductor gate structure which is easy to use and manufacture.